A Merged Memory Logic (MML) device may be a device including a Dynamic Random Access Memory (DRAM) and peripheral circuits integrated on a single chip.
MML has improved the functionality of multimedia and may allow high-integration and high-speed operation of a semiconductor device to be more effectively achieved. In addition, in the field of an analog circuit requiring high-speed operation, a semiconductor device having a mass storage capacitor is being developed.
A capacitor may have a Polysilicon-Insulator-Polysilicon (PIP) structure. In such a situation, a top electrode and a bottom electrode may include conductive polysilicon.
However, a capacitor having such a PIP structure may have various disadvantages. For example, a capacitance may be lowered because natural oxide layers may be formed due to an oxidation reaction occurring at the interfacial surface between the top/bottom electrodes and a dielectric thin film.
Further, due to a depletion region that may be formed in a polysilicon layer, a PIP capacitor may have a lowered capacitance and thus may be unsuitable for high-speed and/or high-frequency operation.
A MIM type capacitor, on the other hand, may be used for high performance semiconductor devices. It may have low resistivity and may not cause parasitic capacitance derived from the depletion.
FIGS. 1A and 1B are example cross-sectional diagrams to illustrate a related art semiconductor and method for fabricating a semiconductor device having an MIM capacitor and a damascene interconnection structure.
Referring to FIG. 1A, first metallic interconnection 15 and second metallic interconnection 20 may be formed on bottom insulating layer 10 of semiconductor substrate 1. First and second metallic interconnections 15 and 20 may not form a step difference relative to bottom insulating layer 10.
A metallic layer may be formed on a resultant structure where first metallic interconnection 15 and second metallic interconnection 20 are formed. The metallic layer may be patterned, and may form bottom electrode 25 of a capacitor making contact with a top surface of second metallic interconnection 20.
Dielectric layer 30 may be formed on a resultant structure including bottom electrode 25. Another metallic layer may then be formed on dielectric layer 30, and may be patterned such that top electrode 35 of the capacitor is formed, for example at a position corresponding to bottom electrode 25. Interlayer dielectric layer 40 may be formed on a resultant structure where top electrode 35 may be formed.
Referring to FIG. 1B, a top surface of interlayer dielectric layer 40 may be planarized, for example by a CMP process. Then, interlayer dielectric layer 40 and dielectric layer 30 may be etched, for example to form via hole V1 that may expose a top surface of first metallic interconnection 15.
First trench T1 may be formed on a top of via hole V1. Second trench T2, that may expose a top surface of top electrode 35, may be formed. Via hole V1 and first and second trenches T1 and T2 may be filled with Cu. A CMP process may then be performed with respect to Cu, and may thereby form a damascene interconnection structure 45 and contact plug 50.
The above described technique may have various problems. For example, a metallic interconnection process for applying a bias voltage to a bottom electrode of the capacitor may be necessary, and a process may become more complex because the via hole and the trench of the top electrode may not be able to be simultaneously formed.
In addition, capacitors may increasingly be important components in a structure of a logic device. Hence, there may be a technical need to improve a capacitance of a capacitor.
There may be several methods for maintaining and/or increasing a capacitance of a capacitor at an appropriate value in a limited unit area, as expressed by the equation C=∈As/d (∈: dielectric constant, As: surface area of electrode, d: thickness of dielectric element). Some of the suggested methods include reducing a thickness of a dielectric element, increasing a surface area of a electrode, and using a material having a high dielectric constant ∈.
With respect to increasing a surface area of an electrode, a related art analog capacitor may use a metallic interconnection as top and bottom electrodes. Accordingly the effective surface area of the related art analog capacitor may be formed as a plane. Hence, there may be a limitation regarding increasing a surface area of the electrode.
FIGS. 2A to 2E are example cross-sectional diagrams to illustrate a related art method for fabricating a semiconductor device having a capacitor and a contact plug between interlayer interconnections.
Referring to FIG. 2A, interlayer dielectric layer 2 may be formed. Metallic conductive layer may be formed and patterned on a top of interlayer dielectric layer 2 such that bottom electrode 4A and bottom interconnection 4B may be formed. A semiconductor substrate (not shown), on which the semiconductor device may be formed, may exist under interlayer dielectric layer 2.
Inter-metallic dielectric layer 6 may be formed and planarized on bottom electrode 4A and bottom interconnection 4B.
Referring to FIG. 2B, contact hole 8 that may expose bottom electrode 4A of the capacitor may be formed by using a known photolithographic process.
Contact hole 8, that may expose bottom electrode 4A, may constitute an effective surface area of the capacitor, so the capacitor may have a large effective surface area.
Referring to FIG. 2C, dielectric layer 10 may be formed on a surface of the substrate including contact hole 8.
Referring to FIG. 2D, via hole 12, that may expose bottom interconnection 4B, may be formed, for example using a known photolithographic process.
Referring to FIG. 2E, a top interconnection conductive layer may be formed and patterned on a surface of semiconductor substrate, and a form top electrode 14A and top interconnection 14B of the capacitor.
The MIM capacitor as described above may be limited as to an increase in capacitance of the capacitor because the effective surface area of the capacitor is formed as a plane.